Density increase of an LSI (Large Scale Integration) has been advanced by making a MOS transistor of its component part smaller in size. With the LSI of the so-called deep sub-micron type in which its component part has the minimum size of 0.5 .mu.m or less, there arises a problem in that the breakdown voltage of the component part is lowered and the power consumption in the LSI is increased. To solve such problems, it is believed as an effective means that the operation voltage is reduced along with miniaturization of the component part.
A 5V-supply voltage is mainly used for the supply voltage of the current LSI, and therefore, the technique by which a voltage conversion circuit for lowering the operating voltage is mounted on an LSI chip is discussed as the means for constructing an LSI by small component parts in "IEEE Journal of Solid-State Circuits", vol. 21, No. 5, pp. 605-611, October 1986. In this case, the values of the external supply voltage and the internal supply voltage are 5 V and 3.5 V, respectively. Thus, there is being actualized the problem of the power consumption in a dynamic RAM (DRAM) with the highest integration out of the LSIs.
On the other hand, however, it is indicated that there is a lower limit in the supply voltage due to physical limitations. Such limitations are discussed in "IEEE Journal of Solid-State Circuits", vol. 9, No. 5, pp. 256-267, October 1974. As indicated in this paper, the low level current characteristics of a MOS transistor include therein the so-called sub-threshold characteristic in which a drain current decreases exponentially in relation to a gate voltage. The coefficient inherent therein is called the sub-threshold coefficient (tailing coefficient) and has a value of the order of 80 mV/decade at room temperature. Accordingly, a problem is encountered in that when the gate threshold voltage is reduced proportionally with the reduction of the supply voltage, a low-level current flows even during the cut-off period of the transistor, thus increasing a current consumption in the stand-by state. For this reason, with the prior art CMOS circuit, it was considered that if the supply voltage is lowered, the threshold voltage cannot be decreased below a predetermined value. This lower limit for the practical application is discussed in "Proceedings of Technical Papers, 1989 International Symposium on VLSI Technology, Systems and Applications", pp. 188-192, May 1989, and "Proceedings of the Symposium on Low Temperature Electronics and High Temperature Superconductors", pp. 55-69, Oct. 1987. That predetermined threshold voltage value is approximately 0.35 to 0.55 V or so. At this time there arises a problem in that the lower limit of the supply voltage is 1.5 V or so in the practical application, and therefore, any further decrease in the voltage will cause a delay time to remarkably increase.